The present invention relates to a noise shaper circuit used in a digital/analog converter of an over-sampling method and, more particularly, to a noise shaper circuit, using a .DELTA. modulation method or a .DELTA..SIGMA. modulation method, for rounding data having an arbitrary number of bits into data having a smaller number of bits.
As a conventional noise shaper circuit used in a digital/analog converter of an over-sampling method, a circuit having characteristics represented by a signal flow graph of a secondary .DELTA..SIGMA. modulator shown in FIG. 2 is generally used. However, when this flow graph is directly realized as a circuit, four calculating circuits 11 to 14 each having a large word length are required, i.e., the circuits 11 to 14 requires a large chip area when the circuits are integrated.
Therefore, as shown in FIG. 3, a circuit in which the number of calculating circuits is decreased to reduce a chip area and a signal flow graph is modified is proposed ("IEEE JOURNAL OF SOLID-STATE CIRCUITS" VOL. SC-22, NO. 3, PP. 390-394, June, 1987). The transfer characteristics of this circuit are the same as those of the circuit in FIG. 2. This circuit of FIG. 3 has three calculating circuits 21, 22, and 23, and the number of calculating circuits is smaller than that of the circuit in FIG. 2. However, when the signal flow graph in FIG. 3 is to be realized in an integrated circuit, the following problem is posed. That is, in processing of data having a large word length, since the wiring lines of the circuit in FIG. 3 are more complicated than those of the circuit in FIG. 2, the data having a large word length requires a large area for data lines. Therefore, the chip area of the integrated circuit is not so reduced.
In FIGS. 2 and 3, reference numerals 15, 16, 18, 24, and 25 denote delay circuits; 17, 28, and 29, quantizers; and 26 and 27, amplitude limiters.
As described above, when a conventional noise shaper circuit is to be realized in an integrated circuit, a chip area is disadvantageously large.